24 lines
549 B
Systemverilog
24 lines
549 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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class C;
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rand bit [3:0] a;
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rand bit [3:0] b;
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// IEEE 1800-2023 18.5.13: the operand of 'disable soft' must be a
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// constraint_primary (hierarchical identifier with optional select),
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// not a bare expression such as (a + 1).
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constraint c_bad {
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disable soft (a + 1);
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}
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endclass
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module t;
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initial begin
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$stop;
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end
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endmodule
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