129 lines
2.1 KiB
Systemverilog
129 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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int x = 0;
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module t;
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int a;
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int b;
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int i;
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int arr[5];
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// function with side effects
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function int foo();
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x += 1;
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return 1;
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endfunction;
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// verilator lint_off ASSIGNEQEXPR
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initial begin
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a = 10;
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i = (a = 2);
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`checkd(a, 2);
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`checkd(i, 2);
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a = 10;
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i = (a += 2);
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`checkd(a, 12);
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`checkd(i, 12);
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a = 10;
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i = (a -= 2);
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`checkd(a, 8);
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`checkd(i, 8);
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a = 10;
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i = (a *= 2);
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`checkd(a, 20);
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`checkd(i, 20);
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a = 10;
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i = (a /= 2);
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`checkd(a, 5);
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`checkd(i, 5);
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a = 11;
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i = (a %= 2);
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`checkd(a, 1);
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`checkd(i, 1);
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a = 10;
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i = (a &= 2);
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`checkd(a, 2);
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`checkd(i, 2);
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a = 8;
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i = (a |= 2);
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`checkd(a, 10);
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`checkd(i, 10);
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a = 10;
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i = (a ^= 2);
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`checkd(a, 8);
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`checkd(i, 8);
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a = 10;
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i = (a <<= 2);
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`checkd(a, 40);
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`checkd(i, 40);
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a = 10;
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i = (a >>= 2);
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`checkd(a, 2);
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`checkd(i, 2);
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a = 10;
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i = (a >>>= 2);
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`checkd(a, 2);
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`checkd(i, 2);
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a = 10;
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i = (a = (b = 5));
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`checkd(a, 5);
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`checkd(i, 5);
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`checkd(b, 5);
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a = 10;
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b = 6;
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i = ((a += (b += 1) + 1));
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`checkd(a, 18);
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`checkd(i, 18);
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`checkd(b, 7);
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arr[0] = 3;
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arr[0] += 4;
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`checkd(arr[0], 7);
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arr[foo()] = 1;
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`checkd(x, 1);
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arr[foo()] += 2;
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`checkd(arr[1], 3);
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`checkd(x, 2);
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arr[foo() + 1] = 6;
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`checkd(x, 3);
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arr[foo() + 1] -= 5;
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`checkd(arr[2], 1);
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`checkd(x, 4);
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i = 0;
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arr[i++] -= 2;
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`checkd(arr[0], 5);
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arr[++i] += 5;
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`checkd(arr[2], 6);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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