verilator/test_regress
Dan Petrisko c5c5f11e16
Tests: Adding failing test case for source synchronous signals (#3038)
2021-07-07 14:00:17 -04:00
..
t Tests: Adding failing test case for source synchronous signals (#3038) 2021-07-07 14:00:17 -04:00
.gdbinit
.gitignore Ignore some files generated by modelsim (#2669) 2020-12-05 21:55:56 -05:00
CMakeLists.txt Add TRACE_THREADS to CMake (#2934) 2021-05-08 08:18:08 -04:00
Makefile Copyright year update 2021-01-01 10:29:54 -05:00
Makefile_obj Copyright year update 2021-01-01 10:29:54 -05:00
driver.pl Tests: fail test if vcddiff aborts, fix failing tests 2021-07-01 23:22:25 +01:00
input.vc
input.xsim.vc