28 lines
710 B
Systemverilog
28 lines
710 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Test module to exercise threshold checking in CFunc inlining
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// With low thresholds, these functions should NOT be inlined
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module t;
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reg [31:0] a, b, c, d, e, f, g, h;
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initial begin
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// Multiple operations to create larger CFuncs
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a = 32'd1;
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b = 32'd2;
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c = a + b;
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d = c * 2;
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e = d - 1;
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f = e + a;
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g = f * b;
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h = g + c + d + e + f;
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if (h != 32'd32) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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