verilator/test_regress
Geza Lore 7225c902ee
Fix V3Life eliminating assignments across timing controls (#6593) (#6596)
For both JumpBlock and Loop, record if they contain a timing control and
do not eliminate assignments across them if so.

Fixes #6593
2025-10-25 21:59:21 +02:00
..
t Fix V3Life eliminating assignments across timing controls (#6593) (#6596) 2025-10-25 21:59:21 +02:00
.gdbinit
.gitignore
CMakeLists.txt
Makefile Testing: Ignore non-deterministic tests in `make test-snap` 2025-10-09 10:34:31 +01:00
Makefile_obj
driver.py Tests: Fix driver.py error for missing scenario (#6586) 2025-10-23 12:48:02 -04:00
input.vc
input.xsim.vc