verilator/bin
Yutetsu TAKATSUKASA 241e54e7b3 Tested with all existing cases after changing the code to split everything.
The following tests fail. Explanation is here.

- Failure because extra warnings
    - vlt/t_a1_first_cc: %Error: Exec of perl failed: No stack.
        make -j && test_regress/t/t_a1_first_cc.pl  --vlt
    - vlt/t_a2_first_sc: %Error: Exec of perl failed: No stack.
        make -j && test_regress/t/t_a2_first_sc.pl  --vlt
    - vlt/t_flag_debugi9: %Error: Exec of perl failed: Starting Verilator 4.029 devel rev v4.028-114-g8e707db3 (mod)
        make -j && test_regress/t/t_flag_debugi9.pl  --vlt
- Failures because the statistics changes
    - vlt/t_split_var_0: %Error: File_grep: obj_vlt/t_split_var_0/Vt_split_var_0__stats.txt: Got='26' Expected='23' in regexp: (?^i:SplitVar,\s+Split unpacked arrays\s+(\d+))
        make -j && test_regress/t/t_split_var_0.pl  --vlt
    - vlt/t_split_var_1_bad: %Error: Line 1 mismatches; obj_vlt/t_split_var_1_bad/vlt_compile.log != t/t_split_var_1_bad.out
        make -j && test_regress/t/t_split_var_1_bad.pl  --vlt
    - vlt/t_split_var_2_trace: %Error: VCD miscompare obj_vlt/t_split_var_2_trace/simx.vcd t/t_split_var_2_trace.out
        make -j && test_regress/t/t_split_var_2_trace.pl  --vlt
    - vlt/t_unopt_combo_isolate: %Error: File_grep: obj_vlt/t_unopt_combo_isolate/Vt_unopt_combo_isolate__stats.txt: Regexp not found: (?^i:Optimizations, isolate_assignments blocks\s+5)
        make -j && test_regress/t/t_unopt_combo_isolate.pl  --vlt
    - vlt/t_unopt_combo_isolate_vlt: %Error: File_grep: obj_vlt/t_unopt_combo_isolate_vlt/Vt_unopt_combo_isolate_vlt__stats.txt: Regexp not found: (?^i:Optimizations, isolate_assignments blocks\s+5)
        make -j && test_regress/t/t_unopt_combo_isolate_vlt.pl  --vlt
    - vlt/t_xml_tag: %Error: Line 26 mismatches; obj_vlt/t_xml_tag/Vt_xml_tag.xml != t/t_xml_tag.out
        make -j && test_regress/t/t_xml_tag.pl  --vlt
- SplitVar changed error message by other pass.
    - vlt/t_bitsel_wire_array_bad: %Error: Line 1 mismatches; obj_vlt/t_bitsel_wire_array_bad/vlt_compile.log != t/t_bitsel_wire_array_bad.out
        make -j && test_regress/t/t_bitsel_wire_array_bad.pl  --vlt
    - vlt/t_lint_multidriven_bad: %Error: Line 9 mismatches; obj_vlt/t_lint_multidriven_bad/vlt_compile.log != t/t_lint_multidriven_bad.out
        make -j && test_regress/t/t_lint_multidriven_bad.pl  --vlt
    - vlt/t_gen_forif: %Error: Exec of perl failed: %Warning-CLKDATA: t/t_gen_forif.v:35: Clock used as data (on rhs of assignment) in sequential block 't.Result'
        make -j && test_regress/t/t_gen_forif.pl  --vlt
    - vlt/t_unoptflat_simple_2_bad: %Error: Exec of perl ok, but expected to fail
        make -j && test_regress/t/t_unoptflat_simple_2_bad.pl  --vlt
- Because of other issue https://github.com/verilator/verilator/issues/1008#issuecomment-581078519
    - vlt/t_select_bound1: %Error: Exec of perl failed: %Error: t/t_select_bound1.v:23: Unsupported: 4-state numbers in this context
        make -j && test_regress/t/t_select_bound1.pl  --vlt
2020-02-12 09:41:44 +09:00
..
verilator Tested with all existing cases after changing the code to split everything. 2020-02-12 09:41:44 +09:00
verilator_coverage Fix shebang breaking some shells. Closes #2067. 2020-01-09 20:01:12 -05:00
verilator_difftree Fix shebang breaking some shells. Closes #2067. 2020-01-09 20:01:12 -05:00
verilator_gantt Fix shebang breaking some shells. Closes #2067. 2020-01-09 20:01:12 -05:00
verilator_includer Fix shebang breaking some shells. Closes #2067. 2020-01-09 20:01:12 -05:00
verilator_profcfunc Fix shebang breaking some shells. Closes #2067. 2020-01-09 20:01:12 -05:00