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47 lines
1.3 KiB
Systemverilog
47 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Unpacked array parameter values with equal elements at different indices are different
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// values, so the instances given them must not share a module specialization.
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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typedef int arr_t[4];
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// Sets one element only, so the constant value has that element and a default for the others
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function automatic arr_t one_hot(int idx);
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one_hot[idx] = 5;
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endfunction
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module sub #(
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parameter arr_t ARR = '{default: 0}
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) (
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output arr_t o
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);
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assign o = ARR;
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endmodule
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module t;
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arr_t o1;
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arr_t o2;
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sub #(.ARR(one_hot(1))) u1 (.o(o1));
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sub #(.ARR(one_hot(2))) u2 (.o(o2));
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// Without $finish, which could come before the outputs: the simulation ends, and runs the final
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// blocks, once time zero has run
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final begin
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`checkd(o1[1], 5);
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`checkd(o1[2], 0);
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`checkd(o2[1], 0);
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`checkd(o2[2], 5);
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$write("*-* All Finished *-*\n");
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end
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endmodule
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