verilator/test_regress/t/t_initial_delay_assign.py

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735 B
Python
Executable File

#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios("simulator_st")
test.compile(timing_loop=True, verilator_flags2=["--timing"])
test.execute(all_run_flags=["+verilator+rand+reset+0"])
test.execute(all_run_flags=["+verilator+rand+reset+1"])
for seed in range(1, 5):
test.execute(all_run_flags=["+verilator+rand+reset+2", f"+verilator+seed+{seed}"])
test.passes()