51 lines
1.5 KiB
C++
51 lines
1.5 KiB
C++
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Nikolai Kumar
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// SPDX-License-Identifier: CC0-1.0
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#include "verilatedos.h"
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#include "verilated.h"
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#include <memory>
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#include VM_PREFIX_INCLUDE
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#include VM_PREFIX_ROOT_INCLUDE
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int main(int argc, char** argv) {
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const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
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const std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{"top"}};
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auto& en = topp->rootp->t__DOT__var_arr__VforceEn;
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auto& val = topp->rootp->t__DOT__var_arr__VforceVal;
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auto& en_a = topp->rootp->t__DOT__var_arr_a__VforceEn;
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auto& val_a = topp->rootp->t__DOT__var_arr_a__VforceVal;
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while (!contextp->gotFinish()) {
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topp->clk = !topp->clk;
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topp->eval();
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if (topp->clk) {
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bool changed = true;
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switch (topp->cyc) {
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case 1:
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en[0][1] = 0x3; val[0][1] = 0x3;
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en_a[0][1] = 0x3; val_a[0][1] = 0x2;
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break;
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case 2:
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en[1][0] = 0x3; val[1][0] = 0x2;
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en_a[1][0] = 0x3; val_a[1][0] = 0x3;
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break;
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case 3:
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en[0][1] = 0x0; en_a[0][1] = 0x0;
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break;
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case 4:
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en[1][0] = 0x0; en_a[1][0] = 0x0;
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break;
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default: changed = false;
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}
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if (changed) topp->eval();
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}
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contextp->timeInc(5);
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}
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return 0;
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}
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