104 lines
1.7 KiB
Systemverilog
104 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop;
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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class obj;
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endclass
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class TypeParams #(
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type T1 = obj,
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type T2 = obj,
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type T3 = obj
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);
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T1 t1;
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T2 t2;
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T3 t3;
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endclass
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class ValueParams #(
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int P1 = 1,
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int P2 = 1,
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int P3 = 1
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);
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logic [P1:0] x1;
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logic [P2:0] x2;
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logic [P3:0] x3;
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endclass
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class Mixed #(
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type T1 = obj,
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int P1 = 1,
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type T2 = obj,
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int P2 = 1,
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type T3 = obj,
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int P3 = 1
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);
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T1 t1;
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T2 t2;
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T3 t3;
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logic [P1:0] x1;
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logic [P2:0] x2;
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logic [P3:0] x3;
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endclass
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module t;
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TypeParams #(
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.T2(int),
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.T3(logic)
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) t;
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obj o;
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ValueParams #(
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.P3(5),
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.P2(2)
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) v;
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Mixed #(
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.P3(3),
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.T1(logic),
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.T3(int),
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.P2(7)
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) m;
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initial begin
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o = new;
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t = new;
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t.t1 = o;
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t.t2 = 32;
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t.t3 = 1;
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if (t.t1 != o) $stop;
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`checkd(t.t2, 32);
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`checkd(t.t3, 1);
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v = new;
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v.x1 = 2;
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v.x2 = 5;
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v.x3 = 40;
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`checkd(v.x1, 2);
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`checkd(v.x2, 5);
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`checkd(v.x3, 40);
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m = new;
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m.t1 = 1;
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m.t2 = o;
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m.t3 = 12345;
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m.x1 = 0;
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m.x2 = 250;
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m.x3 = 15;
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`checkd(m.t1, 1);
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if (m.t2 != o) $stop;
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`checkd(m.t3, 12345);
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`checkd(m.x1, 0);
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`checkd(m.x2, 250);
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`checkd(m.x3, 15);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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