12 lines
320 B
Systemverilog
12 lines
320 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t #(parameter bit fail = 0)();
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if (!(!fail)) begin
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__VnotExising__Vmodule__abc__ sentinel ();
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end
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endmodule
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