66 lines
1.4 KiB
Systemverilog
66 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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interface inf;
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int v;
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endinterface
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module GenericModule1D (interface a[4]);
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initial begin
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#1;
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if (a[0].v != 'hdead) $stop;
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if (a[1].v != 'hbeef) $stop;
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a[2].v = 'hface;
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a[3].v = 'hcafe;
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end
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endmodule
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module GenericModule2D (interface a[2][2]);
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initial begin
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#3;
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if (a[0][0].v != 'hdead) $stop;
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a[0][1].v = 'hbeef;
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if (a[1][0].v != 'hface) $stop;
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a[1][1].v = 'hcafe;
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end
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endmodule
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module GenericModuleRng (interface a[5:3]);
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initial begin
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#5;
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if (a[3].v != 'hdead) $stop;
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if (a[4].v != 'hbeef) $stop;
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a[5].v = 'hface;
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end
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endmodule
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module t;
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inf inf1d[4]();
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inf inf2d[2][2]();
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inf infrng[5:3]();
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GenericModule1D mod1d(inf1d);
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GenericModule2D mod2d(inf2d);
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GenericModuleRng modrng(infrng);
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initial begin
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inf1d[0].v = 'hdead;
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inf1d[1].v = 'hbeef;
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#2;
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if (inf1d[2].v != 'hface) $stop;
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if (inf1d[3].v != 'hcafe) $stop;
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inf2d[0][0].v = 'hdead;
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inf2d[1][0].v = 'hface;
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#2;
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if (inf2d[0][1].v != 'hbeef) $stop;
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if (inf2d[1][1].v != 'hcafe) $stop;
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infrng[3].v = 'hdead;
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infrng[4].v = 'hbeef;
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#2;
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if (infrng[5].v != 'hface) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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