50 lines
1023 B
Systemverilog
50 lines
1023 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checks(gotv, expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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class Cls;
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typedef enum {
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A = 10,
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B = 20,
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C = 30
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} en_t;
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en_t en;
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endclass
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class WideCls;
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typedef enum logic [95:0] {
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A = 96'h1,
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B = 96'h2
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} en_t;
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en_t en;
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endclass
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initial begin
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Cls c;
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WideCls w;
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string s;
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if (c.A != 10) $stop;
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c = new;
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c.en = c.B;
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if (c.en != 20) $stop;
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s = $sformatf("%p", c);
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`checks(s, "'{en:'h14}");
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w = new;
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w.en = w.B;
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s = $sformatf("%p", w);
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`checks(s, "'{en:'h2}");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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