60 lines
1.3 KiB
Systemverilog
60 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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logic clk = 1'b0;
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always #5 clk = ~clk;
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logic rst = 1'b1;
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initial #22 rst = 1'b0;
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logic assertEnable = 1'b0;
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initial #44 assertEnable = 1'b1;
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initial begin
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#1000;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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int cntA = 0;
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int cntB = 100;
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always @(posedge clk) begin
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cntA <= cntA + 1;
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cntB <= cntB + 1;
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end
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// Should combine the 2 assertOn checks after hoisting
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always @(posedge clk) begin
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if (rst) begin
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// Blank
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end else if (assertEnable) begin
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assert (cntA == cntB - 100);
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labelled_A: assert (cntB - cntA == 100);
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end
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end
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// Should combine the 2 assertOn checks after hoisting
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always @(posedge clk) begin
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if (assertEnable) begin
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labelled_B: assert (cntA + 100 == cntB);
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end
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if (!assertEnable) begin
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// Blank
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end else begin
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assert (cntA - cntB == -100);
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end
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end
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endmodule
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