19 lines
435 B
Systemverilog
19 lines
435 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// ======================================================================
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module sub #(
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parameter type TYPE_t = logic
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) (
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input TYPE_t in,
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output TYPE_t out
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);
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// Some simple logic
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always_comb out = ~in;
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endmodule
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