25 lines
613 B
Systemverilog
25 lines
613 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface iface #(
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parameter DWIDTH = 32
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) ();
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localparam TOTAL_PACKED_WIDTH = DWIDTH + 1;
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modport Tx(output sop, data, import unpack);
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logic sop;
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logic [DWIDTH - 1:0] data = '0;
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task static unpack(input logic [TOTAL_PACKED_WIDTH-1:0] packed_in, input logic sop_i);
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logic sop_nc;
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{data, sop_nc} <= packed_in;
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sop <= sop_i;
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endtask
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endinterface
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module t;
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iface ifc ();
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endmodule
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