56 lines
1.4 KiB
Systemverilog
56 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2011 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`begin_keywords "VAMS-2.3"
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module t;
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task check(integer line, real got, real expec);
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real delta;
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delta = got - expec;
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if (delta > 0.001 || delta < -0.001) begin
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$write("Line%0d: Got %g Exp %g\n", line, got, expec);
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$stop;
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end
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endtask
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wreal wr;
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assign wr = 1.1;
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sub sub (.*);
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initial begin
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check(`__LINE__, asin(0.5), 0.523599);
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check(`__LINE__, asinh(0.5), 0.481212);
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check(`__LINE__, atan(0.5), 0.463648);
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check(`__LINE__, atan2(0.5, 0.3), 1.03038);
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check(`__LINE__, atanh(0.5), 0.549306);
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check(`__LINE__, ceil(2.5), 3.0);
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check(`__LINE__, cos(0.5), 0.877583);
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check(`__LINE__, cosh(0.5), 1.12763);
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check(`__LINE__, exp(2.0), 7.38906);
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check(`__LINE__, floor(2.5), 2.0);
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check(`__LINE__, ln(2.0), 0.693147);
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check(`__LINE__, log(2.0), 0.30103);
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check(`__LINE__, pow(2.0, 2.0), 4.0);
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check(`__LINE__, sin(0.5), 0.479426);
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check(`__LINE__, sinh(0.5), 0.521095);
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check(`__LINE__, sqrt(2.0), 1.414);
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check(`__LINE__, tan(0.5), 0.546302);
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check(`__LINE__, tanh(0.5), 0.462117);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub (
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input wreal wr
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);
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initial begin
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if (wr != 1.1) $stop;
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end
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endmodule
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