115 lines
2.2 KiB
Systemverilog
115 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2018 Yu-Sheng Lin <johnjohnlys@media.ee.ntu.edu.tw>
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// SPDX-License-Identifier: CC0-1.0
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module t (
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clk
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`ifndef SYSTEMC
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,fst_inout
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,state
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`endif
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);
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input clk;
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`ifndef SYSTEMC
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output state;
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inout fst_inout;
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`endif
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wire clk;
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wire [4:0] state;
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wire fst_inout;
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int cyc;
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reg rstn;
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parameter real fst_gparam_real = 1.23;
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localparam real fst_lparam_real = 4.56;
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real fst_real = 1.23;
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integer fst_integer;
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bit fst_bit;
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logic fst_logic;
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int fst_int;
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shortint fst_shortint;
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longint fst_longint;
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byte fst_byte;
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time fst_time;
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parameter fst_parameter = 123;
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localparam fst_lparam = 456;
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supply0 fst_supply0;
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supply1 fst_supply1;
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tri0 fst_tri0;
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tri1 fst_tri1;
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tri fst_tri;
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triand fst_triand;
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trior fst_trior;
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//trireg fst_trireg; // Error-UNSUPPORTED
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wand fst_wand;
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wor fst_wor;
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wire fst_wire;
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uwire fst_uwire;
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Test test ( /*AUTOINST*/
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// Outputs
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.state(state[4:0]),
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// Inputs
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.clk(clk),
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.rstn(rstn)
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);
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// Test loop
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always @(posedge clk) begin
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cyc <= cyc + 1;
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fst_time <= $time;
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if (cyc == 0) begin
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// Setup
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rstn <= ~'1;
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end
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else if (cyc < 10) begin
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rstn <= ~'1;
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end
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else if (cyc < 90) begin
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rstn <= ~'0;
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (
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input clk,
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input rstn,
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output logic [4:0] state
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);
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logic [4:0] state_w;
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logic [4:0] state_array[3];
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assign state = state_array[0];
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always_comb begin
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state_w[4] = state_array[2][0];
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state_w[3] = state_array[2][4];
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state_w[2] = state_array[2][3] ^ state_array[2][0];
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state_w[1] = state_array[2][2];
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state_w[0] = state_array[2][1];
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end
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always_ff @(posedge clk or negedge rstn) begin
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if (!rstn) begin
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for (int i = 0; i < 3; i++) state_array[i] <= 'b1;
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end
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else begin
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for (int i = 0; i < 2; i++) state_array[i] <= state_array[i+1];
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state_array[2] <= state_w;
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end
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end
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endmodule
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