60 lines
1.5 KiB
Systemverilog
60 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2009 Iztok Jeras
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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// packed structures
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struct packed {
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logic e0;
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logic [1:0] e1;
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logic [3:0] e2;
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logic [7:0] e3;
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} struct_dsc; // descendng range structure
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/* verilator lint_off ASCRANGE */
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struct packed {
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logic e0;
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logic [0:1] e1;
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logic [0:3] e2;
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logic [0:7] e3;
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} struct_asc; // ascending range structure
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/* verilator lint_on ASCRANGE */
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integer cnt = 0;
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// event counter
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always @(posedge clk) begin
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cnt <= cnt + 1;
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end
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// finish report
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always @(posedge clk)
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if (cnt == 2) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @(posedge clk)
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if (cnt == 1) begin
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// descending range
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if ($bits(struct_dsc) != 15) $stop;
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if ($bits(struct_dsc.e0) != 1) $stop;
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if ($bits(struct_dsc.e1) != 2) $stop;
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if ($bits(struct_dsc.e2) != 4) $stop;
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if ($bits(struct_dsc.e3) != 8) $stop;
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if ($increment(struct_dsc, 1) != 1) $stop;
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// ascending range
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if ($bits(struct_asc) != 15) $stop;
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if ($bits(struct_asc.e0) != 1) $stop;
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if ($bits(struct_asc.e1) != 2) $stop;
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if ($bits(struct_asc.e2) != 4) $stop;
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if ($bits(struct_asc.e3) != 8) $stop;
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if ($increment(struct_asc, 1) != 1) $stop; // Structure itself always big numbered
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end
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endmodule
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