41 lines
910 B
Systemverilog
41 lines
910 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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package TEST_TYPES;
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typedef struct a_struct_t; // Forward
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typedef struct packed {logic stuff;} a_struct_t;
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endpackage // TEST_TYPES
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module t (
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clk
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);
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input clk;
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TEST_TYPES::a_struct_t [3:0] a_out;
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sub sub (.a_out);
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always @(posedge clk) begin
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if (a_out[0] != 1'b0) $stop;
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if (a_out[1] != 1'b1) $stop;
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if (a_out[2] != 1'b0) $stop;
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if (a_out[3] != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub (
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a_out
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);
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parameter N = 4;
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output TEST_TYPES::a_struct_t [N-1:0] a_out;
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always_comb begin
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for (int i = 0; i < N; i++) a_out[i].stuff = i[0];
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end
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endmodule
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// Local Variables:
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// verilog-typedef-regexp: "_t$"
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// End:
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