29 lines
627 B
Systemverilog
29 lines
627 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Outputs
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vlan,
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// Inputs
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clk,
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pkt_data
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);
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parameter WIDTH = 320;
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input clk;
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input [2559:0] pkt_data;
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output reg [15:0] vlan;
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always @(posedge clk) begin
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// verilator lint_off WIDTHCONCAT
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// verilator lint_off WIDTHTRUNC
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vlan <= pkt_data[{(WIDTH-12), 3'b0}-1-:16];
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// verilator lint_on WIDTHCONCAT
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// verilator lint_on WIDTHTRUNC
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end
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endmodule
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