61 lines
1.3 KiB
Systemverilog
61 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Test symbol table scope map and general public
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// signal reflection
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2015 Todd Strader
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input wire CLK
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);
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foo #(.WIDTH(1)) foo1 (.*);
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foo #(.WIDTH(7)) foo7 (.*);
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foo #(.WIDTH(8)) foo8 (.*);
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foo #(.WIDTH(32)) foo32 (.*);
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foo #(.WIDTH(33)) foo33 (.*);
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foo #(.WIDTH(40)) foo40 (.*);
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foo #(.WIDTH(41)) foo41 (.*);
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foo #(.WIDTH(64)) foo64 (.*);
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foo #(.WIDTH(65)) foo65 (.*);
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foo #(.WIDTH(96)) foo96 (.*);
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foo #(.WIDTH(97)) foo97 (.*);
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foo #(.WIDTH(128)) foo128 (.*);
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foo #(.WIDTH(256)) foo256 (.*);
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foo #(.WIDTH(1024)) foo1024 (.*);
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bar #(.WIDTH(1024)) bar1024 (.*);
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endmodule
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module foo #(
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parameter WIDTH = 32
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) (
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input CLK
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);
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logic [( ( WIDTH + 7 ) / 8 ) * 8 - 1 : 0] initial_value;
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logic [WIDTH - 1 : 0] value_q /* verilator public */;
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integer i;
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initial begin
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initial_value = '1;
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for (i = 0; i < WIDTH / 8; i++) initial_value[i*8+:8] = i[7 : 0];
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value_q = initial_value[WIDTH-1 : 0];
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end
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always @(posedge CLK) value_q <= ~value_q;
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endmodule
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module bar #(
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parameter WIDTH = 32
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) (
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input CLK
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);
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foo #(.WIDTH(WIDTH)) foo (.*);
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endmodule
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