51 lines
928 B
Systemverilog
51 lines
928 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Geza Lore
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// SPDX-License-Identifier: CC0-1.0
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`define show(x) $display("oarray[%2d] is %2d", x, oarray[x])
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module t;
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int iarray[63:0];
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int oarray[63:0];
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initial begin
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for (int i = 0; i < 64; i = i + 1) begin
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iarray[i] = i;
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oarray[i] = 0;
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end
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for (int i = 0; i < 63; i = i + 1) begin
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oarray[i] = iarray[i+1];
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end
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$display("shift down 1");
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`show(63);
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`show(62);
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`show(61);
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`show(32);
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`show(2);
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`show(1);
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`show(0);
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for (int i = 63; i >= 2; i = i - 1) begin
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oarray[i] = iarray[i-2];
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end
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$display("shift up 2");
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`show(63);
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`show(62);
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`show(61);
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`show(32);
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`show(2);
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`show(1);
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`show(0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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