38 lines
819 B
Systemverilog
38 lines
819 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2016 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// See issue #1991
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module t (
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input clk
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);
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socket #(3'b000) s0 ();
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socket #(3'b010) s1 ();
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socket #(2'b10) s2 ();
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socket #(2'b11) s3 ();
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always_ff @(posedge clk) begin
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if (s0.ADDR != 0) $stop;
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if (s1.ADDR != 2) $stop;
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if (s2.ADDR != 2) $stop;
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if (s3.ADDR != 3) $stop;
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if ($bits(s0.ADDR) != 3) $stop;
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if ($bits(s1.ADDR) != 3) $stop;
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if ($bits(s2.ADDR) != 2) $stop;
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if ($bits(s3.ADDR) != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module socket #(
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ADDR
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) ();
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initial $display("bits %0d, addr %b", $bits(ADDR), ADDR);
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endmodule
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