34 lines
595 B
Systemverilog
34 lines
595 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2016 Mandy Xu
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// SPDX-License-Identifier: CC0-1.0
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module t #(
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parameter [95:0] P = 1
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) (
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input clk
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);
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localparam [32:0] M = 4;
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function [M:0] gen_matrix;
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gen_matrix[0] = 1 >> M;
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endfunction
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reg [95:0] lfsr = 0;
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always @(posedge clk) begin
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lfsr <= (1 >> P);
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end
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wire [95:0] lfsr_w = 1 >> P;
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localparam [95:0] LFSR_P = 1 >> P;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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