92 lines
2.2 KiB
Systemverilog
92 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2010 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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package some_pkg;
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localparam FOO = 5;
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localparam BAR = 6;
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typedef enum int {QUX = 7} pkg_enum_t;
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endpackage
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module t (
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input clk
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);
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int cyc = 0;
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localparam int unsigned SPI_INDEX = 0;
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localparam int unsigned I2C_INDEX = 1;
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localparam int unsigned TMR_INDEX = 4;
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localparam logic [31:0] AHB_ADDR[6] = '{
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SPI_INDEX: 32'h80001000,
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I2C_INDEX: 32'h80002000,
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TMR_INDEX: 32'h80003000,
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default: '0
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};
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initial begin
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`checkh(AHB_ADDR[0], 32'h80001000);
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`checkh(AHB_ADDR[1], 32'h80002000);
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`checkh(AHB_ADDR[2], 32'h0);
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`checkh(AHB_ADDR[3], 32'h0);
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`checkh(AHB_ADDR[4], 32'h80003000);
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`checkh(AHB_ADDR[5], 32'h0);
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end
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genvar genvar_i;
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for (genvar_i = 0; genvar_i < 2; genvar_i++) begin : the_gen
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logic [31:0] gen_array[10];
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always_comb gen_array = '{genvar_i: 32'habcd, default: 0};
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always_ff @(posedge clk) begin
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`checkh(gen_array[genvar_i], 32'habcd);
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end
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end
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typedef enum int {
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ENUM_A = 0,
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ENUM_B,
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ENUM_C
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} enum_t;
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logic [31:0] enum_array[11];
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always_comb enum_array = '{ENUM_A: 32'h1234, ENUM_B: 32'h7777, ENUM_C: 32'ha5a5, default: 0};
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always_ff @(posedge clk) begin
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`checkh(enum_array[0], 32'h1234);
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`checkh(enum_array[1], 32'h7777);
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`checkh(enum_array[2], 32'ha5a5);
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end
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logic [31:0] package_array[8];
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import some_pkg::*;
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always_comb package_array = '{FOO: 32'h9876, BAR: 32'h1212, QUX: 32'h5432, default: 0};
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always_ff @(posedge clk) begin
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`checkh(package_array[5], 32'h9876);
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`checkh(package_array[6], 32'h1212);
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`checkh(package_array[7], 32'h5432);
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end
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always_ff @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 2) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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