29 lines
562 B
Systemverilog
29 lines
562 B
Systemverilog
// DESCRIPTION: Verilator: Demonstrate complex user typea problem with --x-assign
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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logic [31:0] mem_a[32];
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logic [15:0] mem_b[32];
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int cyc = 0;
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// finish report
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always @(posedge clk) begin
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cyc <= cyc + 1;
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mem_a[cyc] <= cyc;
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mem_b[cyc] <= 16'(cyc);
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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