51 lines
972 B
Systemverilog
51 lines
972 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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interface Bus #(
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parameter int W = 1,
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X = 2
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);
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logic [W-1:0] data;
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endinterface
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interface BusTyped #(
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parameter type T
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);
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T data;
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endinterface
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typedef struct packed {logic x;} my_logic_t;
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module t;
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Bus #(6, 3) intf1 ();
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virtual Bus #(6, 3) vintf1 = intf1;
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Bus intf2 ();
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virtual Bus #(
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.W(1),
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.X(2)
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) vintf2 = intf2;
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BusTyped #(my_logic_t) intf3 ();
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virtual BusTyped #(my_logic_t) vintf3 = intf3;
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initial begin
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intf1.data = '1;
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if (vintf1.data != 6'b111111) $stop;
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if (vintf1.X != 3) $stop;
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intf2.data = '1;
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if (vintf2.data != 1'b1) $stop;
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if (vintf2.X != 2) $stop;
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intf3.data.x = '1;
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if (vintf3.data.x != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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