48 lines
778 B
Systemverilog
48 lines
778 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 1;
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counter_io c_data ();
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counter_ansi c1 (
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.clk,
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.*
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);
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counter_ansi c2 (
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.clk,
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.c_data
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);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 20) begin
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if (c_data.value != 12345) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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interface counter_io;
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integer value;
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endinterface
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module counter_ansi (
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input clk,
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counter_io c_data
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);
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always_ff @(posedge clk) begin
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c_data.value <= 12345;
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end
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endmodule : counter_ansi
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