50 lines
1.0 KiB
Systemverilog
50 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test that a package import declaration can precede a parameter port list
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// in an interface declaration. See IEEE 1800-2023 25.3.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Jeremy Bennett
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// SPDX-License-Identifier: CC0-1.0
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package bus_pkg;
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parameter WIDTH = 8;
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endpackage
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interface simple_bus
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import bus_pkg::*; // Import preceding parameters.
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#(
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p_width = WIDTH
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) (
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input logic clk
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);
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logic req, gnt;
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logic [p_width-1:0] addr;
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logic [p_width-1:0] data;
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modport slave(input req, addr, clk, output gnt, input data);
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modport master(input gnt, clk, output req, addr, output data);
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endinterface
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module mem (
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simple_bus a
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);
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logic avail;
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always @(posedge a.clk) a.gnt <= a.req & avail;
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initial begin
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if ($bits(a.data) != 8) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module t (
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input clk
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);
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simple_bus sb (clk);
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mem mem (sb.slave);
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endmodule
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