76 lines
1.4 KiB
Systemverilog
76 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 1;
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ifc ifc (); // Cell name hides interface's name
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assign ifc.ifi = 55;
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sub sub (.isub(ifc)); // Cell name hides module's name
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int om;
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mod_or_type mot (.*);
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hides_with_type hides_type ();
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hides_with_decl hides_decl ();
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 20) begin
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if (om != 22) $stop;
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if (mot.LOCAL != 22) $stop;
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if (ifc.ifo != 55) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub (
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ifc isub
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);
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always @* begin
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isub.ifo = isub.ifi;
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end
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endmodule
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module mod_or_type (
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output int om
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);
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localparam LOCAL = 22;
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initial om = 22;
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endmodule
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module hides_with_type ();
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typedef int ifc; // Hides interface
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typedef int mod_or_type; // Hides module
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ifc /*=int*/ hides_ifc;
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mod_or_type /*=int*/ hides_mod;
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initial hides_ifc = 33;
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initial hides_mod = 44;
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endmodule
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module hides_with_decl ();
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int ifc; // Hides interface
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int mod_or_type; // Hides module
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initial ifc = 66;
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initial mod_or_type = 77;
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endmodule
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interface ifc;
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localparam LOCAL = 12;
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int ifi;
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int ifo;
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endinterface
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