70 lines
1.4 KiB
Systemverilog
70 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Very simple test for interface pathclearing
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module t (
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input clk
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);
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integer cyc = 1;
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ifc #(1) itopa ();
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ifc #(2) itopb ();
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sub #(1) ca (
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.isub(itopa),
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.i_value(4)
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);
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sub #(2) cb (
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.isub(itopb),
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.i_value(5)
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);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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if (itopa.MODE != 1) $stop;
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if (itopb.MODE != 2) $stop;
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end
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if (cyc == 20) begin
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if (itopa.get_value() != 4) $stop;
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if (itopb.get_value() != 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub #(
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parameter MODE = 0
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) (
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ifc.out_modport isub,
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input integer i_value
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);
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always @* isub.value = i_value;
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endmodule
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interface ifc;
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parameter MODE = 0;
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// Modports under generates not supported by all commercial simulators
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integer value;
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modport out_modport(output value);
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function integer get_value();
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return value;
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endfunction
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// IEEE 1800-2017 deprecated alowing modports inside generates
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// generate if (MODE == 0) begin
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// integer valuea;
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// modport out_modport (output valuea);
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// function integer get_valuea(); return valuea; endfunction
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// end
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endinterface
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