43 lines
830 B
Systemverilog
43 lines
830 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Auto-resolved by t_interface_find_ifc.v
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// interface t_interface_find_ifc;
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module t (
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input clk
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);
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integer cyc = 1;
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t_interface_find_ifc itop ();
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sub c1 (
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.isub(itop),
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.i_value(4'h4)
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);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 20) begin
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if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison
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if (itop.value != 4) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub (
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t_interface_find_ifc isub,
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input logic [3:0] i_value
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);
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always @* begin
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isub.value = i_value;
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end
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endmodule : sub
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