48 lines
914 B
Systemverilog
48 lines
914 B
Systemverilog
// DESCRIPTION: Verilator: Get parameter from array of interfaces
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Todd Strader
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// SPDX-License-Identifier: CC0-1.0
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interface intf #(
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parameter int FOO = 4
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) (
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input wire clk,
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input wire rst
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);
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modport modp(input clk, rst);
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endinterface
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module sub (
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intf.modp the_intf_port[4],
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intf.modp single_intf_port
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);
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localparam intf_foo = the_intf_port[0].FOO;
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localparam single_foo = single_intf_port.FOO;
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initial begin
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if (intf_foo != 4) $stop;
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if (single_foo != 4) $stop;
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end
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endmodule
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module t (
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clk
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);
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logic rst;
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input clk;
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intf the_intf[4] (.*);
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intf single_intf (.*);
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sub the_sub (
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.the_intf_port(the_intf),
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.single_intf_port(single_intf)
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);
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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