39 lines
654 B
Systemverilog
39 lines
654 B
Systemverilog
// DESCRIPTION: Verilator: Connecting an interface array slice to a module's portmap
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2015 Todd Strader
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// SPDX-License-Identifier: CC0-1.0
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interface foo_intf;
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logic a;
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modport m(input a);
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endinterface
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module foo_mod (
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foo_intf foo,
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foo_intf.m bars[4]
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);
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endmodule
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module t;
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localparam N = 4;
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foo_intf foos[N-1:0] ();
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foo_intf bars[N] ();
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//foo_intf foos ();
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foo_mod foo_mod (
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.foo(foos[2]),
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.bars(bars)
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//.foo (foos)
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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