16 lines
451 B
Systemverilog
16 lines
451 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire signed [16:0] fft_oQ[6:0];
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round round (.i_data(fft_oQ[6:0]));
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endmodule
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module round (
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input wire signed [16:0] i_data // Misdeclared, not a vector
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);
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wire signed [15:0] w_convergent = {10'b0, {6{~i_data[7]}}};
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endmodule
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