68 lines
1.3 KiB
Systemverilog
68 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2005 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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parameter ONE = 1;
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wire [17:10] bitout;
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reg [7:0] allbits;
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reg [15:0] onebit;
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sub sub[7:0] (
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allbits,
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onebit,
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bitout
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);
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integer x;
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always @(posedge clk) begin
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//$write("%x\n", bitout);
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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allbits <= 8'hac;
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onebit <= 16'hc01a;
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end
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if (cyc == 2) begin
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if (bitout !== 8'h07) $stop;
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allbits <= 8'hca;
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onebit <= 16'h1f01;
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end
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if (cyc == 3) begin
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if (bitout !== 8'h41) $stop;
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if (sub[0].bitout !== 1'b1) $stop;
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if (sub[1].bitout !== 1'b0) $stop;
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`ifndef verilator // Hacky array subscripting
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if (sub[ONE].bitout !== 1'b0) $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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`ifdef USE_INLINE
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`define INLINE_MODULE /*verilator inline_module*/
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`else
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`define INLINE_MODULE /*verilator public_module*/
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`endif
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module sub (
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input [7:0] allbits,
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input [1:0] onebit,
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output bitout
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);
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`INLINE_MODULE
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assign bitout = (^onebit) ^ (^allbits);
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endmodule
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