39 lines
773 B
Systemverilog
39 lines
773 B
Systemverilog
// DESCRIPTION: Verilator: Demonstrate struct literal param assignment problem
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module sub #(
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parameter int param_a,
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parameter bit [1:0] enum_param = '0
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) ();
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typedef enum logic [1:0] {
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FOO = enum_param,
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BAR,
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BAZ
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} enum_t;
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enum_t the_enum = enum_t'(1);
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initial $display("%s", the_enum.name());
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endmodule
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module t (
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input clk
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);
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// finish report
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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sub #(.param_a(1)) the_sub1 ();
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sub #(.param_a(2)) the_sub2 ();
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sub #(
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.param_a(2),
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.enum_param(2'd1)
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) the_sub3 ();
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endmodule
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