42 lines
1.4 KiB
Systemverilog
42 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0);
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// verilog_format: on
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// Test that rand variables used as array indices in constraints are treated
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// as symbolic in the solver, not evaluated at C++ constraint setup time.
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class RandArrayIndexTest;
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rand bit [1:0] idx;
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rand bit [7:0] data [4];
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rand bit [7:0] selected_value;
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constraint solve_order { solve idx before selected_value; }
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constraint value_match { selected_value == data[idx]; }
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constraint data_values {
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foreach (data[i]) {
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data[i] inside {[8'd10:8'd50]};
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}
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}
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endclass
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module t;
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initial begin
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static RandArrayIndexTest obj = new();
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repeat (20) begin
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`checkd(obj.randomize(), 1)
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`checkd(obj.selected_value, obj.data[obj.idx])
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`check_range(obj.selected_value, 8'd10, 8'd50)
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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