71 lines
1.3 KiB
Systemverilog
71 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Arkadiusz Kozdra
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// SPDX-License-Identifier: CC0-1.0
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typedef class Cls;
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class Wrap #(
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parameter P = 13
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);
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function int get_p;
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return c1.get_p();
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endfunction
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function new;
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c1 = new;
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endfunction
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Cls #(PMINUS1 + 1) c1;
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localparam PMINUS1 = P - 1; // Checking works when last
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endclass
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class Wrap2 #(
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parameter P = 35
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);
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function int get_p;
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return c1.get_p();
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endfunction
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function new;
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c1 = new;
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endfunction
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Wrap #(PMINUS1 + 1) c1;
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localparam PMINUS1 = P - 1; // Checking works when last
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endclass
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class Cls #(
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parameter PBASE = 12
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);
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bit [PBASE-1:0] member;
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function bit [PBASE-1:0] get_member;
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return member;
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endfunction
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static function int get_p;
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return PBASE;
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endfunction
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typedef enum {E_PBASE = PBASE} enum_t;
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endclass
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typedef Cls#(8) Cls8_t;
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module t;
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Cls c12;
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Cls #(.PBASE(4)) c4;
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Cls8_t c8;
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Wrap #(.P(16)) w16;
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Wrap2 #(.P(32)) w32;
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Wrap2 #(Wrap #(19)::PBASE * 2) w38;
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initial begin
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c12 = new;
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c4 = new;
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c8 = new;
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w16 = new;
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w32 = new;
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w38 = new;
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if (w38.get_p() != 38) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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