43 lines
761 B
Systemverilog
43 lines
761 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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class Foo #(
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type T = bit
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);
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int x = $bits(T);
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endclass
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class Bar #(
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type S = int
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) extends Foo #(S);
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endclass
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typedef Bar#() bar_default_t;
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class Baz;
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Bar #(logic [7:0]) bar_string;
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int bar_x;
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function new;
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bar_string = new;
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bar_x = bar_string.x;
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endfunction
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endclass
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typedef Baz baz_t;
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module t;
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initial begin
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automatic bar_default_t bar_default = new;
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automatic baz_t baz = new;
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if (bar_default.x != 32) $stop;
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if (baz.bar_x != 8) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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