73 lines
1.2 KiB
Systemverilog
73 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off NORETURN
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class c0 #(
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type T = real
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);
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static function T f();
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endfunction
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endclass
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class c2 #(
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type REQ = int,
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type RSP = int,
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type IMP = int
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);
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function new(IMP imp);
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endfunction
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endclass
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class c3 #(
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type REQ,
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type RSP,
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type IMP = RSP
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);
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function new(IMP imp);
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endfunction
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endclass
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class c1 #(
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type REQ = int,
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RSP = REQ
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);
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typedef c1#(REQ, RSP) this_type;
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typedef c0#(this_type) type_id;
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c2 #(REQ, RSP, this_type) c2inst;
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function new(string name, int parent);
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c2inst = new(this);
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endfunction
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c3 #(REQ, this_type) c3inst;
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endclass
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`define test \
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c1 #(real) c1inst1;\
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c1 #(real, real) c1inst2;\
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c1 #(real, int) c1inst3;\
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c1 #() c1inst4;\
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c1 c1inst5;
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`test
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interface interf;
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// `test
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endinterface
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module t;
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// `test
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interf interf_inst ();
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endmodule
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class topc;
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// `test
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endclass
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class paramcl;
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endclass : paramcl
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class c5;
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c1 #(paramcl) seq;
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function void f();
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seq = c1#(paramcl)::type_id::f();
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endfunction : f
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endclass
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c5 c5inst;
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