51 lines
1.1 KiB
Systemverilog
51 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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typedef struct {
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string path;
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int offset;
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int size;
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} uvm_hdl_path_slice;
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class ral_reg;
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function void add_hdl_path(uvm_hdl_path_slice slices[], string kind = "RTL");
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foreach (slices[i]) begin
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$display("Add %s", slices[i].path);
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end
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endfunction
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endclass
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class Cls;
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rand ral_reg m_counters[4];
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function new();
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foreach (this.m_counters[i]) begin
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this.m_counters[i] = new;
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end
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endfunction
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function void build();
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foreach (this.m_counters[i]) begin
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int J = i;
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// this.m_counters[J] = ral_reg_slave_B1_COUNTERS::type_id::create(
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// $sformatf("COUNTERS[%0d]", J),, get_full_name());
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this.m_counters[J].add_hdl_path('{'{$sformatf("COUNTERS[%0d]", J), -1, -1}});
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end
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endfunction
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endclass
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initial begin
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Cls c;
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c = new;
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c.build;
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$finish;
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end
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endmodule
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