69 lines
1.9 KiB
Systemverilog
69 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int cyc;
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int cntneg;
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logic rst_l;
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wire [1:0] req = cyc[2:1];
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wire gnt = cyc[0];
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// verilator lint_off MULTIDRIVEN
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logic assert_procedural;
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logic assert_immediate;
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wire logic assert_exp = (req == 2'b11) && !gnt && rst_l;
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// verilator lint_off MULTIDRIVEN
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always @(negedge clk) begin
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assert property (disable iff (!rst_l) ((&req) |-> gnt))
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else
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assert_procedural <= 1'b1;
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cntneg <= cntneg + 1; // To check unlink of above assert
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end
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assert property (@(negedge clk) disable iff (!rst_l) ((&req) |-> gnt))
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else
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assert_immediate <= 1'b1;
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d req='b%b gnt=%b exp=%x proc=%x imm=%x\n", $time, cyc, req, gnt, assert_exp, assert_procedural, assert_immediate);
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`endif
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cyc <= cyc + 1;
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assert_procedural <= 0; // Careful, will race unless assert is on negedge
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assert_immediate <= 0; // Careful, will race unless assert is on negedge
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if (cyc == 0) begin
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// Setup
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rst_l <= !1'b1;
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end
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else if (cyc < 10) begin
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`checkh(assert_procedural, assert_exp);
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`checkh(assert_immediate, assert_exp);
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end
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else if (cyc == 19) begin
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rst_l <= !1'b0;
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end
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else if (cyc < 30) begin
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`checkh(assert_procedural, assert_exp);
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`checkh(assert_immediate, assert_exp);
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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