25 lines
480 B
Systemverilog
25 lines
480 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t();
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logic clk = 0;
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logic out = 1;
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always #5 clk = ~clk;
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initial begin
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while(1) begin
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if(out) begin
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break;
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end
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@(negedge clk);
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end
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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