22 lines
465 B
Systemverilog
22 lines
465 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int loops;
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initial begin
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#1;
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// verilator lint_off INFINITELOOP
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while (1'b1) begin
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$write("*-* All Finished *-*\n");
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$finish; // Infinite loop, but for this finish
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if (++loops > 100) $stop;
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end
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end
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endmodule
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