26 lines
517 B
Systemverilog
26 lines
517 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic never;
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integer n = 0;
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initial begin
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disable fork;
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fork
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#10 if (n != 0) $stop; else n = 1;
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#15 if (n != 1) $stop; else n = 2;
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join_none
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wait fork;
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if (n != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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