36 lines
825 B
Systemverilog
36 lines
825 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2010 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [31:0] count /*verilator public_flat_rd */;
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integer status;
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// Test loop
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initial begin
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count = 0;
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end
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$display("[%0t] clk", $time);
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`endif
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count <= count + 2;
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if (count == 1000) begin
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// See C++ code: $write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule : t
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