20 lines
426 B
Systemverilog
20 lines
426 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`include "verilated.v"
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module t;
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initial begin
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`verilator_file_descriptor i;
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`coverage_block_off
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i = $fopen("/dev/null", "r");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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