23 lines
407 B
Systemverilog
23 lines
407 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Anthony Donlon
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire a, b;
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udp i_udp (a, b);
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endmodule
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primitive udp #(
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parameter A = 1
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) (o, a);
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output o;
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input a;
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table
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//o a
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0 : 1;
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1 : 0;
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endtable
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endprimitive
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